Semiconductor memory using dynamic ram cells

ABSTRACT

Bit-line pairs and word lines are disposed perpendicular to one another and dRAM cells are placed at their intersections. A dummy cell is connected to each of the bit-line pairs. A bit-line sense amplifier and an equalizer are connected to one end of the bit-line pair. The other end of the bit-line pair is connected to a latch type memory cell via a first transfer gate. The latch type memory cell are further connected to input/output line pair via a second transfer gate controlled by a column select line. During a RAS active period in a read cycle a word line is selected so that data is read from a dRAM cell and the dummy cell connected to the selected word line onto the bit-line pairs. The bit-line sense amplifiers are activated so that the levels of the bit lines become determinate. The first transfer gates are subsequently turned on to transfer the data on the bit-line pairs to the latch type cells. After the memory cells are rewritten into, the selected word line is reset and the latch type memory cells are electrically disconnected from the bit-line pairs. The equalizers operate to precharge the bit-line pairs. When CAS is rendered active and a column is selected, a corresponging second transfer gate is turned on so that data in the latch type memory cell is read out onto the input/output line pairs.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated semiconductor memories usingdynamic RAMs (dRAMs) containing dynamic memory cells for destructivereadout.

2. Description of the Related Art

Recently many inventions and developments have been made to speed upsemiconductor memories. The semiconductor memories include dRAMs andsRAMs (static RAMs). The dRAMs are superior to the sRAMs in storagecapacity and cost, but inferior in speed. The reason why the dRAMs areinferior to the sRAMs in speed is that the dRAMs are increased inintegration density by the use of an address multiplexing method inorder to decrease their cost per bit. The fact that dRAMs needrefreshing and bit-line precharging because they are of destructive-readtype may also be attributed to their low-speed operation. With computersusing the sRAMs as their main memories, their machine cycle isdetermined only by an access time to the sRAM. Where the dRAMs are usedas main memories, the machine cycle is determined by their access timeand bit-line precharging time.

For that reason, in the conventional dRAMs, various operation modes,such as a page mode, a nibble mode and a static column mode, have beendeveloped to shorten the access time.

However, a problem with the conventional dRAMs is that, even if theaccess time is reduced in a normal access mode, the cycle time is not soreduced. For example, with a 1M-bit dRAM having an access time of 100nsec in the normal access mode, the cycle time is 190 nsec in itsspecification because it is a sum of an active time and the prechargingtime. Even if the access time is reduced by half, the cycle time willnot be halved unless the precharging time is also reduced by half. Thedifficulty in reducing the precharging time is due not only to the factthat the capacitive loads of bit lines to be charged have been increasedto increase the storage capacity of the dRAMs, but also to the fact thatthe bit lines are precharged and equalized during a precharging periodin which an RAS signal (row address strobe signal for loading the rowaddress into the memory device) goes from a logic "0" to a logic "1",not during an active period to read or write data.

Where semiconductor memories are installed in computers, the length ofmachine cycle is an important factor in the performance of thecomputers. In the static RAMs, since the access time and the cycle timecoincide with each other, the reduction of the access time will alsoreduce the machine cycle. In the dynamic RAMs, however, the reduction ofthe access time alone will not lead to the reduction of the machinecycle.

In the conventional dRAMs of address multiplexing type, there is nodistinction between a read cycle and a write cycle because an addressdata selector is controlled by a CAS signal (column address strobe forloading the column address into the memory device) only. That is, duringan active cycle, a row address strobe (RAS) is input into the dRAM priorto the CAS. The row address and the column address are issued in thissequence from the address data selector and then entered into a dRAMchip. To secure operational margin surely, a certain time is needed fromwhen the RAS is made active until the CAS is made active. It is thusdifficult to shorten the cycle time of the dRAMs and hence the machinecycle of computers using the dRAMs.

As described above, the conventional dRAMs have a problem that thereduction of the access time does not lead to the reduction of the cycletime, and thus the machine cycle of the computers using the dRAMs cannotbe reduced.

SUMMARY OF THE INVENTION

It is a first object of the present invention to provide a semiconductormemory using a dRAM which saves the need for a precharging time for bitlines, which is conventionally separate from an access time, and thusreduces its cycle time.

It is a second object of the present invention to provide a dRAMsemiconductor memory of address-multiplexing type which enables ahigh-speed write operation.

It is a third object of the present invention to provide a dRAMsemiconductor memory with divided bit-line structure which saves theneed for a precharging time for bit lines and thus reduces its cycletime.

The first object is achieved by connecting a latch means to bit linesand initiating precharging of the bit lines after, during a RAS activetime period, data is transferred from a memory cell connected to aselected word line to the latch means via the bit lines.

The second object is achieved by, in an address multiplexing dRAMsemiconductor memory, loading a column address first by inputting a CAS,and then a row address by inputting a RAS in both a read cycle and awrite cycle and writing data into a bit line pair or a circuitimmediately preceding the bit line pair during the write cycle.

The third object is achieved by, in a dRAM semiconductor memory of adivided bit-line configuration, connecting a latch means between mainbit lines and input/output lines and transferring data between the dRAMand the outside while precharging the main bit lines and sub bit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a semiconductor memory device according toa first embodiment of the present invention;

FIG. 2 is a circuit diagram of a portion of the first embodiment;

FIGS. 3A and 3B show waveforms of signals indicating the operation in areadout cycle of the first embodiment;

FIG. 4 shows a first modification of a latch-type memory cell of thefirst embodiment;

FIG. 5 shows a second modification of the latch-type memory cell of thefirst embodiment;

FIG. 6 shows a third modification of the latch-memory cell of the firstembodiment;

FIG. 7 shows a fourth modification of the latch-type memory cell of thefirst embodiment;

FIG. 8 is a block diagram of a semiconductor memory according to asecond embodiment of the present invention;

FIGS. 9A, 9B, and 9C show waveforms of signals indicating an operationin a readout cycle of the second embodiment;

FIGS. 10A, 10B, 10C, and 10D show waveforms of signals indicating theoperation in a write cycle of the second embodiment;

FIGS. 11A and 11B show waveforms of signals indicating the operation ina readout cycle of a third embodiment;

FIGS. 12A and 12B show waveforms of signals indicating the operation ina write cycle of the third embodiment;

FIG. 13 is a block diagram of a semiconductor memory according to afourth embodiment of the present invention;

FIG. 14 is a circuit diagram of a portion of the fourth embodiment;

FIGS. 15A and 15B show waveforms of signals indicating the operation ina readout cycle of the fourth embodiment;

FIGS. 16A and 16B show waveforms of signals indicating the operation ina write cycle of the fourth embodiment;

FIGS. 17A and 17B are a block diagram of a semiconductor memoryaccording to a fifth embodiment of the present invention;

FIG. 18 is a circuit diagram of a portion of the fifth embodiment;

FIGS. 19A and 19B show waveforms of signals indicating the operation ina readout cycle of the fifth embodiment;

FIGS. 20A and 20B are a block diagram of a semiconductor memoryaccording to a sixth embodiment of the present invention;

FIG. 21 is a circuit diagram of a portion of the sixth embodiment;

FIGS. 22A and 22B show waveforms of signals indicating the operation ina readout cycle of the sixth embodiment; and

FIGS. 23A and 23B show waveforms of signals indicating the operation ina write cycle of the sixth embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, there is shown the overall structure of a firstembodiment of the present invention. Over a semiconductor substrate notshown, plural pairs of bit lines BLi, BLi (i=1˜m) and plural word linesMWj (j=1˜n) are disposed perpendicular to each other and dRAM cells MCijare placed at their intersections. Each dRAM cell MCij is selectivelydriven by word line MWj so that data is transferred between bit linesBLi and BLi. In addition to the dRAM cells, dummy cells DCi1 and DCi2are coupled to bit-line pair BLi and BLi of each row. Dummy cells DCi1and DCi2 are driven by dummy word lines DW1 and DW2, respectively.

A bit-line sense amplifier 10-i is coupled to ends of bit lines BLi, BLifor each of rows in order to detect the level of data read out onto BLiand BLi.

To equalize and precharge bit lines BLi, BLi, an equalizer 50-i iscoupled to sense amplifier 10-i. Equalizer 50-i is connected with abit-line precharging power supply VBL and also supplied with anequalizing signal EQL1.

The other ends of bit lines BLi, BLi are coupled to a latch type memorycell (hereinafter, is called as latch memory cell) 20-i via a firsttransfer gate 30-i which is supplied with a control signal φT. Latchmemory cell 20-i is supplied with activation signals φCE and φCE.Outputs of latch memory cell 20-i are coupled to input/output lines I/Oand I/O via a second transfer gate 40-i which is supplied with a columnselect signal CSLi.

FIG. 2 shows a specific arrangement of the dRAM of FIG. 1, particularlya detailed circuit diagram for one row. The dRAM cell MC and dummy cellDC are of a well known type comprised of one transistor and onecapacitor. A reference potential terminal of the capacitor is connectedto a plate power supply VPL. Dummy cells DCi1 and DCi2 include n channelMOS transistors Q9 and Q10, respectively, which are connected to aprecharging power supply VDC, for data-writing.

Bit line amplifier 10-i is comprised of a pair of n channel MOStransistors Q4 and Q5 and another pair of p channel MOS transistors Q6and Q7. Activation signals φSE and φSE applied are to the respectivepairs of Q4, Q5 and Q7, Q8 at their sources connected in common.

Equalizer 50-i is comprised of three n-channel MOS transistors Q1, Q2,Q3 which are supplied at their gates with equalize signal EQL1.Transistors Q1 and Q2 are adapted for precharging and have their sourcesconnected to bit lines BLi and BLi, respectively, with their drainsconnected to precharging power supply VBL in common. Transistor Q3 isadapted for equalizing and have its source and drain connected to bitlines BLi and BLi, respectively.

Latch memory cell 20-i includes a flip-flop comprised of a pair of nchannel MOS transistors Q18 and Q19 and a flip-flop comprised of a pairof p channel MOS transistors Q21 and Q22. Activation signals φCE andφCE, acting as latch clocks, are applied to the common sourceconnections of the transistor pairs, respectively. Q20 is an n-channelMOS transistor used for equalizing.

Nodes Ai and Ai of latch memory cell 20-i described above are coupled tobit lines BLi, BLi via n channel MOS transistors Q16 and Q17,respectively, which form first transfer gate 30-i. On the other hand,nodes Ai and Ai are also coupled to input/output lines I/O and IO via nchannel MOS transistors Q23 and Q24, respectively, which form secondtransfer gate 40-i. First transfer gate 30-i is controlled by controlsignal φT, while second transfer gate 40-i is controlled by columnselect signal CSLi selected by a column address.

The operation of the dRAM with such an arrangement as described abovewill be described hereinafter.

FIGS. 3A and 3B are a timing diagram showing the operation during a readcycle. Here, an operation, in a system in which bit lines BLi and BLiare precharged to (1/2) VDD, for transferring data in latch memory cell20-i to input/output lines I/O and I/O will be indicated.

In the beginning of operation, since bit-line equalize signal EQL1 is atthe VDD level and precharging power supply VBL provides (1/2) VDD volts,all of the bit lines BL and BL are precharged to (1/2) VDD. Assume nowthat VDD (logic "1") is written into a node N1 between capacitor C3 andtransistor Q12 of dRAM cell MCi1 associated with the i-th bit lines BLiand BLi. Furthermore, assume that a node N3 between capacitor C2 andtransistor Q11 of dummy cell DCi2 is initially set to (1/2) VDD level bywrite power supply VDC.

When the RAS goes from logic "1" level (VIH) to logic "0" level (VIL),the operation goes into an RAS active mode. As a result, equalizesignals EQL1 and EQL2 go from VDD volts down to VSS volts so that bitlines BLi and BLi are electrically disconnected from each other, andnode N3 of dummy cell DCi2 assumes a floating state.

Subsequently, for example, when word line MW1 is selected and this lineand dummy word line DW2 are raised to (3/2) VDD level, the stored datain dRAM cell MCi1 and dummy cell DCi2 are read out onto bit lines BLiand BLi, respectively. At the same time, equalize signal EQL3 of latchmemory cell 20-i decreases from VDD volts to VSS volts.

Subsequently, n-channel transistor activation signal φSE decreases from(1/2) VDD volts to VSS volts, and then p-channel transistor activationsignal φSE increases from (1/2) VDD volts to VDD volts. As a result, bitline BLi onto which logic "1" data has been read out is raised to VDD,while bit line BLi to which data in dummy cell DCi2 has been read out islowered to VSS.

Control signal φT subsequently goes from VSS to VDD causing firsttransfer gate 30-i to turn on. When activation signal φCE goes from(1/2) VDD to VSS and φCE goes from (1/2) VDD to VDD, the contents of bitlines BLi and BLi are transferred to nodes Ai and Ai of latch memory20-i.

At a time when the data on bit lines BLi and BLi are thus transferredinto latch memory cell 20-i, if a write trigger signal WE generatedoutside the dRAM chip is at logic "1" and hence the operation is in aread mode, then the bit-line precharge will be initiated automatically.The precharge operation will be described next.

After memory cell MCi1 selected for readout has sufficiently beenrestored (rewritten), selected word line MWi1 and dummy word line DW2are lowered in potential from (3/2)VDD to VSS causing latch memory cell20-i to be electrically disconnected from bit lines BLi and BLi.

Bit-line equalize signal EQL1 goes from VSS to VDD causing equalizer 10to precharge the bit lines. In this case, when CAS clock goes from logic"1" to logic "0", if the i-th column is selected, column select signalCSLi is raised in level from VSS to VDD or (3/2) VDD causing secondtransfer gate 40-i to turn on and nodes Ai and Ai of latch memory cell20-i to be electrically connected to input/output lines I/O and I/O.When the i-th column is selected, I/O remains at VDD, I/O is loweredfrom VDD to VSS, and an output terminal Dout (not shown) connected toinput/output lines I/O and I/O goes from high-impedance level (Hiz) tologic "1" level (VOH).

If the column select signal CSLi goes to VDD when control signal φT isat VDD and first transfer gate 30-i in the on state, bit lines BLi andBLi and nodes Ai and Ai of latch memory cell 20-i are simultaneouslyelectrically connected to input/output lines I/O and I/O, in which casethe data on bit lines BLi and BLi are directly read out ontoinput/output lines I/O and I/O.

As described above, according to the present invention, by the provisionof a latch memory cell at ends of bit lines in order to temporally storedata read out of a dRAM cell, the bit lines can be precharged during aRAS active time. That is, the latch memory cell, which enables data tobe read from or written into during a bit-line precharge time, isprovided between the paired bit lines and the input/output lines, andwhen the RAS goes from logic "1" to logic "0", a word line is selectedso that data in the dRAM cell is transferred to the latch memory. Inthis case, if the CAS is pulled down to logic "0" prior to the RAS, acolumn select line can be selected to read out data to the outsideimmediately after the selection of the word line. Thereafter by turningoff the transfer gate between the bit lines and the latch memory cell,the bit lines can be precharged while the RAS remains at logic "0". Inother words, precharging the bit lines can be performed during a RASactive time, which has been performed in the prior art during a RASprecharge time other than the RAS active time. As a result, the cycletime can be shortened. This is very effective for speeding up computersusing large-capacity dRAMs as their main memories.

In the above embodiment, the precharged level of the bit lines is (1/2)VDD. Alternatively, the precharged level may be VDD. BICMOS circuits(circuits using a combination of bipolar transistors and CMOStransistors) may be used in the sense amplifier and its peripheralcircuits. Furthermore, latch memory cell 20-i may be modified in variousways as shown in FIGS. 4 through 7.

FIG. 4 shows a first modification of the latch memory cell 20-i which ismodified such that precharging n-channel MOS transistors Q25 and Q26 areadded. The drains of transistors Q25 and Q26 are connected together toprecharging power supply VLC. The transistors are controlled by equalizesignal EQL3 so that the nodes Ai and Ai of the latch memory cell 20-iare initially set to VLC (e.g., (1/2) VDD). As precharging power supplyVLC the precharging power supply VBL for the bit lines may be used.

In a second modification of FIG. 5, p-channel MOS transistors Q21 andQ22 of the first embodiment are replaced with load resistances R1 andR2, respectively, for connection to VDD. Resistances R1 and R2 may beformed of polysilicon, for example. In this modification, the initiallevel of activation signal φCE is chosen to be VDD so that nodes Ai andAi are initially set to the VDD level.

FIG. 6 shows a third modification which uses n-channel MOS transistorsQ27 and Q28 in place of resistances R1 and R2 of FIG. 5. In this case,transistors Q27 and Q28 are of enhancement type and each act as a loadwith drain and gate connected together. As a result, the initial levelof nodes Ai and Ai will be set to VDD-Vth. Vth stands for the thresholdvoltage of Q27, Q28.

FIG. 7 shows a fourth modification which uses n-channel MOS transistorsQ29 and Q30 of depletion type as loads. In this case, transistors Q29and Q30 each have its gate connected to its source. In this arrangement,the initial level of nodes Ai and Ai will be set to VDD.

A second embodiment of the present invention will be described next. Thesecond embodiment is arranged to precharge, like the first embodiment,bit lines in an address-multiplexing type dRAM. That is, a read cycleand a write cycle are made different from each other in the inputsequence of an row address and a column address. The overall blockdiagram is shown in FIG. 8. The arrangement of the dRAM is the same asthat in the first embodiment and thus the description thereof isconsidered to be unnecessary.

Referring to FIG. 8, an address data selector 170 is connected between adRAM chip 160 and a CPU 180. Address data applied from CPU 180 toaddress data selector 170 has 2n bits. The n high-order bits of theaddress data are used as a column address and the n low-order bits as arow address. Address data selector 170 in turn applies the columnaddress and the row address to address inputs A1-An of dRAM chip 160.

Address data selector 170 has a select control terminal SEL adapted todetermine which of the column address and the row address is to beoutput first. The level of a signal applied to select control terminalSEL is determined by a gate circuit 190 according to a combination oflevels of RAS, CAS and WE. When among RAS, CAS and WE, RAS first goesfrom logic "1" to logic "0", gate circuit 190 applies a signal of logic"1" to control terminal SEL. When control terminal SEL is at logic "1"level, address data selector 170 issues the row address first. Afterthat, CAS goes to logic "0" level causing control terminal SEL to go tologic "0" level. As a result, the column address is issued from addressdata selector 170. The above relates to a read cycle.

For a write cycle, on the other hand, CAS and WE go to logic "0" levelprior to RAS and thus the control signal from gate circuit 190 goes tologic "0", causing the column address to be issued first. Subsequently,RAS goes to logic "0" level, causing the row address to be issued fromaddress data selector 170.

It is to be noted here that delay circuits D1 and D2 are connected toRAS and CAS input terminals, respectively, of dRAM chip 160. This is toprovide a setup time for an input address to dRAM chip 160.

The operation of the dRAM of the second embodiment described above willbe described hereinafter.

Referring to FIGS. 9A, 9B, and 9C, there are shown timing diagrams ofthe operation during a read cycle. As in the first embodiment, theoperation, in the system where bit lines BL and BL are precharged to(1/2) VDD, to transfer the data in latch memory 20-i onto input/outputlines I/O, I/O while the bit lines are being precharged is here shown.However, unlike the first embodiment, data is transferred serially.

In the beginning of operation, since equalize signal EQL1 is at the VDDlevel and bit-line precharging power supply VBL is at the (1/2) VDDlevel, all the bit lines BL and BL have been precharged to (1/2) VDD.Assume now that a logic "1" (VDD) is written into storage node N1 ofdRAM cell MCi1 associated with i-th bit lines BLi and BLi of interestand storage node N3 of dummy cell DCi2 is initially set to (1/2) VDD bywrite power supply VDC.

When the RAS goes from logic "1" level (VIH) to logic "0" level (VIL),the operation goes into an RAS active mode. As a result, equalizesignals EQL1 and EQL2 go from VDD volts down to VSS volts so that bitlines BLi and BLi are electrically disconnected from each other, andnode N3 of dummy cell DCi2 assumes a floating state.

Subsequently, for example, when word line MWl is selected and this lineand dummy word line are raised to (3/2) VDD level, the stored data indRAM cell MCi1 and dummy cell DCi2 are read out onto bit lines BLi andBLi, respectively. Thereafter, equalize signal EQL3 of latch memory cell20-i decreases from VDD volts to VSS volts.

Subsequently, n-channel transistor activation signal φSE decreases from(1/2) VDD volts to VSS volts, and then p-channel transistor activationsignal φSE goes from (1/2) VDD to VDD. As a result, bit line BLi ontowhich logic "1" data has been read out is raised to VDD, while bit lineBLi to which data in dummy cell DCi2 has been read out is lowered toVSS.

Subsequently, control signal φT goes from VSS to VDD causing firsttransfer gate 30-i to turn on. When activation signal φCE goes from(1/2) VDD to VSS and φCE goes from (1/2) VDD to VDD, the contents of bitlines BLi and BLi are transferred to nodes Ai and Ai of latch memory20-i.

At a time when the data on bit lines BLi and BLi are thus transferredinto latch memory cell 20-i, if the write trigger signal WE generatedoutside the dRAM chip is at logic "1" and hence in a read mode, then thebit-line precharge will be initiated automatically. The prechargeoperation will be described next.

After memory cell MCi1 selected for readout has sufficiently beenrestored (rewritten), selected word line MWi1 and dummy word line DW2are lowered in potential from (3/2) VDD to VSS so that MCi1 goes into anonselected state. Afterward latch memory cell 20-i is electricallydisconnected from bit lines BLi and BLi.

Bit-line equalize signal EQL1 goes from VSS to VDD causing equalizer10-i to to precharge the bit lines. In this case, when CAS clock goesfrom logic "1" to logic "0", if the i-th column is selected, columnselect signal CSLi is raised in level from VSS to VDD or (3/2) VDDcausing second transfer gate 40-i to turn on and nodes Ai and Ai oflatch memory cell 20-i to be electrically connected to input/outputlines I/O and I/O. When the i-th column is selected, I/O remains at VDD,I/O is lowered from VDD to VSS, and the output terminal Dout goes fromhigh-impedance level (Hiz) to logic "1" level (VOH). The operationdescribed so far is the same as that of the first embodiment.

Subsequently, when RAS is in the logic "0" state and CAS goes from logic"0" back to logic "1", the data at output terminal Dout is reset to Hiz.The data of sense amplifier 10-i is also reset and I/O, which has beenlowered to VSS, is also precharged to the VDD level like I/O. A columnaddress buffer and a column decoder are also reset, and column selectsignal CSLi goes from VDD to VSS.

Afterward, when the j-th column address is entered and CAS again goesfrom logic "1" to logic "0", the j-th column select line CSLj isselected. The content in the j-th latch memory cell, which is logic "0"now, is read out so that the output terminal Dout goes from Hiz to logic"0" (VOL).

Moreover, CAS is set from logic "0" to logic "1" to perform CASprecharging, and then the k-th column address is entered to render CASactive with the result that the data in the k-th latch memory cell, inthis case logic "1", is read out.

When RAS is raised from logic "0" to logic "1" and CAS is subsequentlyraised from logic "0" to logic "1", equalize signal EQL3 goes from VSSto VDD, resetting data in all the latch memory cells 20.

As is evident from the foregoing, according to the second embodiment,during the read cycle, by temporally storing data read from a memorycell in the latch memory cell and by toggling the CAS, the serial accesscan be performed while the bit lines are precharged during the RASactive period.

The write-cycle operation will be described with reference to timingcharts of FIGS. 10A, 10B, 10C, and 10D. Unlike the read cycle, duringthe write cycle, the CAS goes from logic "1" to logic "0" prior to theRAS. At the same time, the WE also goes to logic "0". As a result, acolumn address is first entered in the dRAM chip. For example, where thei-th column is selected, the column select signal CSLi does not rise atthis time, but the column address is latched into the column decoder forselecting a column select line. The writing circuitry operates toactivate a sense amplifier associated with the input/output lines I/Oand I/O. In this case the I/O goes from VDD to VSS, while the I/Oremains at VDD.

Subsequently, when the RAS clock goes from logic "1" to logic "0", theequalize signals EQL1, EQL2 and EQL3 go from VDD down to VSS with theresult that the bit lines BLi, BLi and the nodes Ai, Ai of the latchmemory cell go into the floating state.

When the level of word line MWi1 and dummy word line DWi2 is raised fromVSS to (3/2) VDD by the entered row address, column select signal CSLiis raised from VSS to VDD by the column address which has already beenlatched into the column decoder and the control signal φT also goes fromVSS to VDD. Consequently, first and second transfer gates 30 and 40 areturned on, and bit lines BLi and BLi are thus electrically connected toinput/output lines I/O and I/O, respectively, so that bit line BLi islowered from (1/2) VDD to VSS and bit line BLi is raised from (1/2) VDDto VDD.

Subsequently, the n-channel transistor activation signal φSE forbit-line sense amplifier 10-i and the activation signal φCE for thelatch memory cell go from (1/2) VDD to VSS, and then the p-channeltransistor activation signal φSE and the latch-memory activation signalφCE go from (1/2) VDD to VDD. As a result, writing data into theselected memory cell and rewriting data into non-selected memory cellsare initiated. That is, since node N1 of the selected dRAM cell MCi1 andnode N3 of dummy memory cell DCi2 are electrically connected to bitlines BLi and BLi, respectively, node N1 goes from VDD to VSS so thatlogic "0" is written into it, and node N3 goes from (1/2) VDD to VDD.

Next, when RAS and WE are in the "0" state, the CAS goes from logic "0"to logic "1", resetting output terminal Dout and the sense amplifier.Like the I/O, the I/O, which has been lowered to VSS, is also prechargedto VDD. At the same time, the column address buffer and column decoderare also reset, and the column select signal CSLi goes from VDD to VSS.

Afterward, when the j-th column address is entered and the CAS goes fromlogic "1" to logic "0" again, the j-th column select line CSLj isselected. At the same time, data is output to output terminal Dout and,if input data is logic "1", then the "1" data is written into a selectedmemory cell of the j-th column.

Moreover, like the above, by causing the CAS to go from logic "0" tologic "1" to perform the CAS precharge, the column address buffer,column decoder output terminal Dout and sense amplifier are reset.

When the k-th column address is entered and the CAS goes from logic "1"to logic "0" to start the CAS active period, "0" data is written into aselected memory in the k-th column. Then, when WE goes from logic "0" tologic "1" while the RAS and CAS are at logic "0", word line MW1 anddummy word line DW2 are lowered from (3/2) VDD to VSS, resulting in thenon-selected state. At almost the same time, control signal φT is alsolowered from VDD to VSS so that first transfer gate 30-i is turned offand thus the latch memory cell is electrically disconnected from the bitlines. The bit-line equalize signal EQL1 then goes from VSS to VDD,initiating the precharging of the bit lines. At the same time, equalizesignal EQL2 goes from VSS to VDD, writing the initial set level of (1/2)VDD into the dummy cell.

By the WE being changed from logic "0" to logic "1", the write circuitryis disabled and instead the read circuitry is enabled so that data inthe k-th latch memory cell is read out from output terminal Dout. In thepresent case, since the logic "0" has been written, logic "0" is output.

As described above, according to the second embodiment utilizing thearrangement in which a latch memory cell is provided for each bit line,the CAS is activated prior to the RAS in the write cycle so that acolumn address may be entered into the dRAM chip prior to a row address,while RAS is activated prior to the CAS in the read cycle so that a rowaddress may be entered into the dRAM chip prior to a column address.Thus, the bit lines are precharged during the RAS active period in theread cycle. In the write cycle, the bit lines can be prechargedimmediately after the write trigger signal WE goes from logic "0" tologic "1" to complete the write cycle.

Moreover, the serial access can be performed by toggling the CAS ineither of the write cycle and the read cycle.

That is to say, since the bit lines can be precharged during the RASactive period, not during the RAS precharge period as in the prior art,the cycle time can be reduced significantly as compared to the priorart.

A third embodiment of the present invention will be describedhereinafter. The circuit arrangement of this embodiment is the same asthat of the first embodiment shown in FIGS. 1 and 2 and thus thedescription thereof is considered unnecessary.

The operation in the read cycle of the third embodiment will bedescribed with reference to FIGS. 11A and 11B. FIGS. 11A and 11B alsoshow signal waveforms in performing an operation to transfer data inlatch memory 20-i onto the input/output lines in the system where thebit lines are precharged to (1/2) VDD.

In the beginning of operation, since bit-line equalize signal EQL1 is atthe VDD level and bit-line precharging power supply VBL is at the (1/2)VDD level, all the bit lines BL and BL have been precharged to (1/2)VDD.

Assume now that a logic "1" (VDD) is written into storage node N1 ofdRAM cell MCi1 associated with i-th bit lines BLi and BLi of interestand storage node N3 of dummy cell DCi2 is initially set to (1/2) VDD bywrite power supply VDC.

When the CAS goes from logic "1" (VIH) to logic "0" (VIL) prior to theRAS, a column address is first entered into the chip. Where, forexample, the i-th column is selected, although column select line CSLidoes not rise from VSS to VDD at this time, the i-th column address islatched into a decoder (not shown) for column select lines.

Subsequently, when the RAS goes from logic "1" to logic "0", equalizesignals EQL1 and EQL2 are lowered from VDD to VSS so that word line MW1is selected and this line and dummy word line DW2 are raised to (3/2)VDD. As a result, the contents of dRAM cell MCi1 and dummy cell DCi2 areread out onto bit lines BLi and BLi, respectively. In addition, equalizesignal EQL3 of latch memory cell 20-i is lowered from VDD to VSS.

The n-channel transistor activation signal φSE of bit-line senseamplifier 10-i subsequently decreases from (1/2) VDD to VSS, and thenp-channel transistor activation signal φSE goes from (1/2) VDD to VSS.As a result, bit line BLi onto which the logic "1" data of memory cellMCi1 has been read out is raised to VDD, while bit line BLi to which thedata in dummy cell DCi2 has been read out is lowered to VSS.

Control signal φT subsequently goes from VSS to VDD causing firsttransfer gate 30 to be turned on. When activation signal φCE goes from(1/2) VDD to VSS and φCE goes from (1/2) VDD to VDD, the contents of bitlines BLi and BLi are transferred to nodes Ai and Ai of latch memory20-i, respectively.

By the column address latched by the decoder for column select lines,column select line CSLi is raised from VSS to VDD so that nodes Ai andAi are electrically connected to input/output lines I/O and I/O,respectively. In the present case, the I/O remains at VDD and I/O islowered from VDD to VSS so that output terminal Vout goes from Hiz toVOH (high level). At the same time, control signal φT goes from VDD toVSS, turning transfer gate 30-i off. After latch memory cell 20-i isthus electrically disconnected from bit lines BLi and BLi, word line MW1and dummy word line DW2 go from (3/2) VDD to VSS and bit-line equalizesignal EQL1 goes from VSS to VDD, precharging the bit lines.

As is evident from the foregoing, in the dRAM of this embodiment also,by temporally storing data read from a memory cell in the latch memorycell associated with the bit lines, the bit lines can be prechargedduring the RAS active period as well.

FIGS. 12A and 12B show signal waveforms for explaining the operation ofthe write cycle. As in the read cycle, in the write cycle as well, theCAS goes from logic "1" to logic "0" prior to the RAS and thus the i-thcolumn address is latched into the decoder for column select lines.

When the write trigger signal WE goes from "1" to "0", the writecircuitry is enabled so that a data input buffer operates to activatethe sense amplifier associated with the input/output lines I/O and I/O.For example, if input data is "0", then the I/O goes from VDD to VSS andthe I/O remains at VDD.

When the RAS then goes from "1" to "0", equalize signals EQL1˜EQL3 gofrom VDD to VSS so that bit lines BLi and BLi and nodes Ai and Ai of thelatch memory cell go into the floating state. The level of word line MW1and dummy word line DW2 is raised from VSS to (3/2) VDD by the input rowaddress. At the same time, column select line CSLi is raised from VSS toVDD by the column address which has already been latched by the columndecoder, and control signal φT also goes from VSS to VDD. As a result,first and second transfer gates 30-i, 40-i are turned on so that bitlines BLi and BLi are electrically connected to input/output lines I/Oand I/O, respectively. The BLi goes from (1/2) VDD to VSS, while the BLigoes from (1/2) VDD to VDD.

Next, n-channel transistor activation signal φSE for the sense amplifierand latch-memory activation signal φCE simultaneously go from (1/2) VDDto VSS, while p-channel transistor activation signal φSE an latch-memoryactivation signal φCE simultaneously go from (1/2) VDD to VDD.Consequently, writing of data into a selected memory cell and rewritingof nonselected memory cells are initiated. That is, since node N1 of theselected dRAM cell MCi1 and node N2 of dummy memory cell DCi2 areconnected to bit lines BLi and BLi, respectively, node N1 goes from VDDto VSS so that logic "0" is written into, and node N2 goes from (1/2)VDD to VDD.

After nonselected memory cells have sufficiently been rewritten, wordline MW1 and dummy word line DW2 go from (3/2) VDD to VSS. Atsubstantially the same time, control signal φT also goes from VDD to VSSand thus transfer gate 30-i turns off, thereby electricallydisconnecting the latch memory from the bit lines. Bit-line equalizesignal EQL1 goes from VSS to VDD so that the precharging of the bitlines is initiated. At the same time, equalize signal EQL2 goes from VSSto VDD so that the initial set level of (1/2) VDD is written into thedummy cell.

In that way, during the read cycle, since data to be written into islatched into the latch memory cell a little early, the timing of thesubsequent precharging of the bit lines can also be quickened.

As described above, according to the third embodiment in which a latchmemory cell is provided for each bit line, the CAS is activated prior tothe RAS and a column address is loaded into the dRAM chip prior to a rowaddress in both the write cycle and the read cycle. Hence, in the readcycle, the bit lines can be precharged while the read data is outputfrom the latch memory. In other words, the precharging of the bit lines,which was conventionally performed during the RAS precharging period,can be performed during the RAS active period. During the write cycle, acolumn select line is selected simultaneously with the selection of aword line, permitting quick writing of data. Immediately after thecompletion of the write cycle, the bit lines are precharged. As a resultof the above, the cycle time can significantly be reduced as comparedwith the prior art.

FIG. 13 shows an arrangement of the dRAM of the fourth embodiment of thepresent invention. The descriptions of the same portions as those of thefirst embodiment shown in FIG. 1 are omitted. In the fourth embodiment,latch memory cell 20-i in the first embodiment is excluded and firsttransfer gate 30-i connected to bit lines BLi and BLi is connected to alatch-type bit-line sense amplifier 10-i via a write transfer gate 60-i.That is, the bit-line sense amplifier serves as the latch memory cell aswell. Nodes Bi and Bi between first transfer gate 30-i and writetransfer gate 60-i serve as write nodes which are connected toinput/output lines I/O and I/O, respectively, via second transfer gate40-i controlled by column select line CSLi. Reset circuit 70-i isconnected to latch-type bit-line sense amplifier 10-i.

FIG. 14 shows a specific circuit arrangement for one row of the dRAM ofFIG. 13.

Bit-line sense amplifier 10-i is comprised of a flip-flop consisting ofa pair of n-channel MOS transistors Q18 and Q19 and a flip-flopconsisting of a pair of p-channel MOS transistors Q21 and Q22. Thesources of paired transistors Q18, Q19 are connected to receiveactivation signal φCE, while the source of paired transistors Q21, Q22are connected to receive activation signal φCE. Equalizing n-channel MOStransistor Q20 of sense amplifier 10-i in the first embodiment isprovided to precede second transfer gate 40-i.

Write transfer gate 60-i between nodes Ai, Ai of sense amplifier 10-iand write nodes Bi, Bi is formed of n-channel MOS transistors Q40, Q41.

A reset circuit 70-i for the sense amplifier 10-i is comprised of twon-channel MOS transistors Q42, Q43 having their drains connectedtogether to bit-line precharge power supply VBL and their sourcesconnected to bit lines BLi, BLi, respectively, and an n-channel MOStransistor Q44 having its source and drain connected to bit lines BLiand BLi, respectively. A reset signal SP is applied to the gates oftransistors Q42, Q43, and Q44.

FIGS. 15A and 15B show signal waveforms used for explaining theoperation in a read cycle of the dRAM of the fourth embodiment. In thisembodiment also, the bit lines are precharged to (1/2) VDD. Further,after stored data in a memory cell is transferred to bit-line senseamplifier 10-i, sense amplifier 10-i is electrically disconnected fromthe bit lines, and data latched into the sense amplifier is transferredto the input/output lines for readout while the bit lines are beingprecharged. The read operation will be detailed hereinafter.

At first since bit-line equalize signal EQL1 is at VDD and bit-lineprecharging power supply VBL is at (1/2) VDD, all the bit lines havebeen precharged to (1/2) VDD. Assume now that VDD or VDD-Vth (logic "1")is written into capacitor node N1 of memory cell MCi1 associated withthe i-th bit-line pair of interest. Capacitor node N3 of dummy cell DCi2is initially set to (1/2) VDD or (1/2) (VDD-Vth).

When RAS goes from logic "1" (VIH) to logic "0" (VIL) prior to CAS sothat the operation goes into the RAS active period, signals EQL1, EQL2,SP, EQL3 go from VDD to VSS and the level of word line MW1 and dummyword line DM2 is raised from VSS to (3/2) VDD or VDD. As a result, thecontents of memory cell MCi1 and dummy cell DCi2 are read out onto bitlines BLi and BLi, respectively. At the same time control signal φT forfirst transfer gate 30-i also goes from VSS to VDD or (3/2) VDD. Sincecontrol signal φW for write transfer gate 60-i remains at VDD or (3/2)VDD, data on bit lines BLi and BLi are transferred to nodes Ai and Aivia write nodes Bi and Bi.

Subsequently n-channel transistor activation signal φCE goes from (1/2)VDD to VSS, and then p-channel transistor activation signal φCE goesfrom (1/2) VDD to VSS. As a result, bit line BLi onto which logic data"1" has been read out from memory cell MCi1 is raised to VDD, while bitline BLi associated with dummy cell DCi2 is lowered to VSS.

After the memory cell associated with selected word line MW1 hassufficiently been rewritten into, word line MW1 and dummy word line DW2are lowered from (3/2) VDD or VDD to VSS so that the cells go into thenonselected state. At the same time since control signal φT is loweredto VSS, first transfer gate 30-i is also turned off so that senseamplifier 10-i is electrically disconnected from bit lines BLi and BLi.Then bit-line equalize signal EQL1 and dummy-cell equalize signal EQL2go from VSS to VDD, beginning equalizing and precharging BLi, BLi anddummy cells DCi1, DCi2. The sequence of operations of selecting a wordline, transferring data to the sense amplifier and latching the datatherein, resetting the word line, electrically disconnecting thebit-line sense amplifier and precharging the bit lines is automaticallyperformed by RAS going from logic "1" to logic "0".

Independently of the series of operations performed so far, CAS goesfrom logic "1" to "0" so that a column address is loaded and thus datais transferred between the bit-line sense amplifier and the input/outputlines in a selected column. That is, assuming now that the i-th columnis selected, column select line CSLi goes from VSS to VDD or (3/2) VDDwith the result that second transfer gate 40-i is turned on and writenodes Bi and Bi are electrically connected to input/output lines I/O andI/O. In this example, I/O remains at VDD, and I/O goes from VDD to VSS,causing output terminal Dout to go from Hiz to logic "1" (VOH).

Afterward, when RAS goes from logic "0" to logic "1" and CAS alsosubsequently goes from logic "0" to "1", reset signal SP for thebit-line sense amplifier and equalize signal EQL3 for the senseamplifier go from VSS to VDD, activation signals φCE and φCE for thebit-line sense amplifier return to (1/2) VDD, and the bit-line senseamplifiers are all reset. Further, column select line CSLi also goesfrom VDD or (3/2) VDD to VSS, input/output lines I/O and I/O return toVDD after being precharged, and output terminal Dout is reset to the Hizlevel.

FIGS. 16A and 16B show signal waveforms used for explaining theoperation of a write cycle of the dRAM of the present embodiment. Duringthe write cycle, CAS goes from logic "1" to logic "0" prior to RAS, andat the same time write trigger signal WE also becomes logic "0".Consequently, a column address is first loaded into the dRAM chip. Atthe same time, bit-line equalize signal EQL1 goes from VDD to VSS sothat the bit line pair goes into the floating state. At the same timedummy-cell equalize signal EQL2 and sense-amplifier equalize signal EQL3also go from VDD to VSS.

If, for example, the i-th column is selected by the column address, thencolumn address CSLi goes from VSS to VDD or (3/2) VDD, turning secondtransfer gate 40-i on. At the same time first transfer gate 30-i is alsoturned on by the rise of control signal φT. Write transfer gate 60-i isturned off by control signal φT going from VDD or (3/2) VDD to VSS withthe result that bit-line sense amplifier 10-i is electricallydisconnected from bit lines BLi and BLi. At the same time the writecircuitry operates, and if write input data is "0", the data inputbuffer is enabled to activate sense amplifier 10-i. In this case, I/Ogoes from VDD to VSS, while I/O immediately returns to VDD after beingslightly lowered because electrons flow into the bit line BLi.

In this way the input data is transferred from input/output lines I/Oand I/O to bit lines BLi and BLi via first and second transfer gates30-i and 40-i. Bit line BLi goes from (1/2) VDD to VSS, while bit lineBLi goes (1/2) VDD to VDD or VDD-Vth.

Thereafter, when RAS goes "1" to "0", the row address buffer operates sothat a row address is loaded. Assuming now that the first word line isselected by the row address, word line MW1 and dummy word line DW2 go inlevel from VSS to (3/2) VDD or VDD.

Subsequently reset signal SP for the bit-line sense amplifier goes fromVDD to VSS, and control signal φW for write transfer gate 60-i goes fromVSS to VDD or (3/2) VDD.

When n-channel transistor activation signal φCE goes from (1/2) VDD toVSS, and p-channel transistor activation signal φCE subsequently goesfrom (1/2) VDD to VDD, nonselected bit lines BLh and BLh go from (1/2)VDD to VDD-Vth (or VDD) and VSS, respectively, according to data fromthe memory cell and dummy cell.

After the memory cell connected to selected word line MW1 is thensufficiently rewritten into, word line MW1 and dummy word line DW2 gofrom (3/2) VDD to VSS so that they go into the nonselected state.Bit-line equalize signal EQL1 and dummy-cell equalize signal EQL2 gofrom VSS to VDD initiating the equalizing and precharging of the bitlines.

Thereafter, write trigger signal WE, RAS and CAS go from logic "0" tologic "1", resetting column select line CSLi, input/output lines I/O andI/O, write nodes Bi and Bi and bit-line sense amplifier 10-i.

In FIGS. 15 and 16, control signal φT for first transfer gate 30-i andcontrol signal φW are shown with VDD as their "H" level. If their "H"level is chosen to be (3/2) VDD, bit lines BLi and BLi go to VDD, VSS.Thus, the "1" write level for memory cells is not VDD-Vth, but VDD.Further, if only up to VDD-Vth is written into a memory cell, the wordline need not be raised and VDD may be used as the "H" level.

As described above, according to the fourth embodiment, a latch-typesense amplifier is provided for each bit line, a write transfer gate isprovided between write nodes and the sense amplifier, and first andsecond transfer gates are provided between the write nodes and the bitlines and between the write nodes and the input/output lines,respectively. Hence, during the read cycle data can be transferredbetween the bit-line sense amplifier and the input/output lines whilethe bit lines are being precharged with the read data latched in thesense amplifier. The precharging of the bit lines can, therefore, beperformed during the RAS active period, reducing the cycle timesignificantly as compared to the prior art. During the write cycle, onthe other hand, the bit lines and the input/output lines areelectrically connected to each other, with the sense amplifierelectrically disconnected from the bit lines, so that data on theinput/output lines can directly be transferred to the bit lines and amemory cell is written into which is selected by a word line selected bya row address. Particularly by causing the CAS to go from "1" to "0"prior to the RAS, a quick write operation is performed, and then the bitlines are precharged.

FIGS. 17A and 17B show the overall structure of the dRAM according to afifth embodiment of the present invention in which a divided bit-linestructure is applied to the dRAM of the third embodiment. On asemiconductor substrate a plurality of paired main bit lines BLi and BLiand a plurality of word lines MWij are disposed perpendicular to eachother. To each pair of main bit lines BLi and BLi are connected aplurality of paired divided bit lines DBij and DBij via correspondingselect gates 80-ij. A plurality of dRAM cells Mij1, Mij2, . . . and twodummy cells Dij1, Dij2 are provided for each pair of divided bit linesDBij and DBij. A divided bit-line latch-type sense amplifier 10-ij isprovided for each pair of divided bit lines DBij and DBij. Main bit-linepair BLi and BLi have their one end connected to main bit-line equalizer50-i and their other end connected to latch memory cell 20-i via firsttransfer gate 30-i. Nodes Ai and Ai of latch memory cell 20-i areconnected to input/output lines I/O and I/O via second transfer gate40-i.

FIG. 18 shows a specific arrangement of the dRAM of the fifthembodiment, particularly of one row associated with the i-th main bitline pair BLi and BLi. Divided bit-line sense amplifier 10-ij includes aflip-flop comprised of a pair of n-channel MOS transistors Q5, Q6 andanother flip-flop comprised of a pair of p-channel MOS transistors Q6,Q7. Activation signals φSEj and φSEj are applied to the sourceconnections of the transistor pairs, respectively. Divided bit-linesense amplifier 10-ij is additionally provided with a divided bit-lineequalize circuit comprised of n-channel transistors Q50, Q51, and Q52connected to receive equalize signal EQL4j.

Main bit-line equalize circuit 50-i is comprised of n-channel MOStransistors Q1, Q2, and Q3. The sources of transistors Q1 and Q2 areconnected to main bit lines BLi and BLi, respectively, and the drainsthereof are connected to precharge power supply VBL. The gates oftransistors Q1, Q2, and Q3 are supplied with main bit-line equalizesignal EQL1.

Select gate 80-ij is comprised of n-channel MOS transistors Q54 and Q55whose gates are supplied with a divided bit-line select signal DSj. Inthe other respects, the dRAM of the fifth embodiment is the same as thefirst embodiment.

The read operation of the dRAM constructed above will be described withreference to FIGS. 19A and 19B. The Figure also shows signal waveformsfor the case where the main bit lines and the divided bit lines areprecharged to (1/2) VDD, and data in the latch memory cell istransferred to the input/output lines for read operation while the mainbit lines and the divided bit lines are being precharged.

First, since main bit-line equalize signal EQL1 is at VDD and bit-lineprecharge power supply VBL is at (1/2) VDD, main bit lines BLi and BLiare all precharged to (1/2) VDD. Similarly, divided bit lines DBij andDBij are all precharged to (1/2) VDD because divided bit-line equalizesignal EQL4j is at VDD.

Assume now that VDD (logic "1") is written into capacitor node N1 ofdRAM cell Mij1 associated with the j-th divided bit-line pair DBij andDBij of interest for the i-th main bit line pair BLi and BLi. Inaddition capacitor node N3 of dummy cell Dij2 is initially set to (1/2)VDD by write power supply VBL.

When the RAS goes from logic "1" (VIH) to logic "0", the operation goesinto the RAS active mode. When equalize signals EQL1, EQL4j, EQL2 gofrom VDD to VSS and the level of word line MWj1 selected by a rowaddress and dummy word line DWj2 goes from VSS to (3/2) VDD, thecontents of dRAM cell Mij1 and dummy cell Dij2 are transferred todivided bit lines DBij and DBij, respectively. At the same time equalizesignal EQL2 for the latch memory cell goes from VDD to VSS.

Thereafter n-channel transistor activation signal φSE for dividedbit-line sense amplifier 10-ij goes from (1/2) VDD to VSS and p-channeltransistor activation signal φSE subsequently goes from (1/2) VDD toVDD. Consequently, divided bit line DBij onto which logic "1" data wasread out is raised to VDD, while divided bit line DBij onto which dataof dummy cell Dij2 was read out is lowered to VSS.

While divided bit lines DBij and DBij make transistors toward VDD andVSS, respectively, divided bit-line select signal DSj and first transfergate control signal φT go from VSS to VDD with the result that data ondivided bit lines DBij and DBij are transferred to nodes Ai and Ai oflatch memory cell 20-i via main bit lines BLi and BLi.

Thereafter latch memory cell activation signal φCE goes from (1/2) VDDto VDD, while activation signal φCE goes from (1/2) VDD to VSS. Duringthat transfer of data, main bit lines BLi and BLi make the respectivetransitions to VDD and VSS. Before the complete transitions of the mainbit lines, control signal DSj for select gate 80-ij and control signalφT for first transfer gate 30-i are lowered from VDD to VSS so as toelectrically disconnect divided bit lines DBij and DBij and latch memorycell 20-i from main bit lines BLi and BLi. This is done to speed up thelatch operation, to reduce the power dissipation and to speed up therewrite (restore) operation for the dRAM cells.

The disconnected main bit lines BLi and BLi are precharged to (1/2) VDDbecause main bit-line equalize signal EQL1 goes from VSS to VDD.Depending on the array arrangement and the memory capacitance, thecapacitance of the main bit lines will be above 2pF in the case of a16-Mbit dRAM, for instance. The restoring of the dRAM cells by thedivided bit lines and latching of data by the latch memory cell underthe condition of connection of the main bit-line capacitance would notonly take a time but also require the large dissipation of power inorder to charge and discharge main bit lines BLi and BLi to VDD and VSS.In this respect, this embodiment is arranged to precharge main bit linesBLi and BLi before the transitions thereof to VDD and VSS, resulting inreduced power dissipation. The final precharged levels of main bit linesBLi and BLi are (1/2) VDD+α and (1/2) VDD-α, respectively. α may beabout (1/10) VDD.

Thereafter divided bit lines DBij and DBij go to VDD and VSS,respectively. After dRAM cells have sufficiently been restored, selectedword line MWj1 and dummy word line DWj2 are lowered from (3/2) VDD toVSS, going into nonselected state.

Divided bit line equalize signal EQLj and dummy cell equalize signalEQL2 subsequently go from VSS to VDD, beginning the equalizing andprecharging of the divided bit lines.

A series of operations of selecting the word line, operating the dividedbit-line sense amplifier, transferring data to the latch memory cell,precharging the main bit lines, resetting the word line and prechargingthe divided bit lines is automatically performed by the RAS going fromlogic "1" to "0".

Independently of the above operation, when, for example, the i-th columnis selected by the CAS going from "1" to "0", column select line CSLigoes from VSS to VDD or (3/2) VDD, electrically connecting nodes Ai andAi to input/output lines I/O and I/O. In this case, I/O remain at VDD,while I/O goes from VDD to VSS, changing output terminal Dout from Hizto logic "1" level.

The RAS subsequently goes from "0" to "1". When CAS goes from "0" to "1"in this state, latch memory cell activation signals φCE and φCE returnto the former (1/2)VDD, resetting all the latch memory cells.

As described above, according to the fifth embodiment of the presentinvention, a plurality of divided bit-line pairs are connected to a mainbit-line pair, dRAM cells are connected to each divided bit-line pair, alatch memory cell is connected to the main bit-line pair. Data can,therefore, be transferred between the dRAM chip and the outside duringthe precharge period. Hence, since there is no need for the RASprecharge period, the cycle time can be shortened. In addition, thelatch operation of the latch memory cell and the rewrite operation forthe dRAM cells by means of the divided bit lines can be speeded up, andsince the main bit lines need not be charged or discharged completely,the power dissipation can be reduced.

FIGS. 20A and 20B show an arrangement of a portion of a dRAM accordingto a sixth embodiment of the present invention. According to thisembodiment, write gates are added to the arrangement of the fifthembodiment in order to electrically disconnecting a latch memory cell20-i from bit lines BLi and BLi at a time of writing data. FIG. 20A isidentical to FIG. 17A. As shown in FIG. 20B, a write gate 60-i isconnected to precede latch memory cell 20-i of the fifth embodiment.

FIG. 21 shows a detailed circuit diagram for one row of the sixthembodiment, particularly of a row connected to the i-th main bit linesBLi and BLi. Write gate 60-i is comprised of n-channel MOS transistorsQ40, Q41 and Q60. The gates of transistors Q40 and Q41 are supplied withφW and the gate of transistor Q60 is supplied with φw. The remainingconfiguration is the same as the configuration of FIG. 18.

The operation of the dRAM constructed above will be described withreference to FIGS. 22A and 22B. These Figures also show signal waveformsfor the case where the main bit lines and the divided bit lines areprecharged to (1/2) VDD, and data in the latch memory cell istransferred to the input/output lines for read operation while the mainbit lines and the divided bit lines are being precharged.

First, since main bit-line equalize signal EQL1 is at VDD and bit-lineprecharge power supply VBL is at (1/2) VDD, main bit lines BLi and BLiare all precharged to (1/2) VDD. Similarly, divided bit lines DBij andDBij are all precharged to (1/2) VDD because divided bit-line equalizesignal EQL4j is at VDD.

Assume now that VDD (logic "1") is written into capacitor node N1 ofdRAM cell Mij1 associated with the j-th divided bit-line pair DBij andDBij of interest for the i-th main bit-line pair BLi and BLi. Inaddition, capacitor node N3 of dummy cell Dij2 is initially set to (1/2)VDD by write power supply VBL.

When the RAS goes from logic "1" (VIH) to logic "0" (VIL) prior to CAS,the operation goes into the RAS active period. In this period, equalizesignals EQL1, EQL4j, EQL2 go from VDD to VSS and the level of word lineMWj1 and dummy word line DWj2 selected by a row address goes from VSS to(3/2) VDD. As a result, the contents of dRAM cell Mij1 and dummy cellDij2 are transferred to divided bit lines DBij and DBij, respectively.At the same time equalize signal EQL3 for the latch memory cell goesfrom VDD to VSS.

Thereafter n-channel transistor activation signal φSE for dividedbit-line sense amplifier SAij goes from (1/2) VDD to VSS and p-channeltransistor activation signal φSE subsequently goes from (1/2) VDD toVDD. Consequently, divided bit line DBij onto which logic "1" data wasread out is raised to VDD, while divided bit line DBij onto which dataof dummy cell Dij2 was read out is lowered to VSS.

While divided bit lines DBij and DBij make transitions toward VDD andVSS, respectively, divided bit-line select signal DSij and firsttransfer gate control signal φT go from VSS to VDD with the result thatdata on divided bit lines DBij and DBij are transferred to write nodesCi and Ci of latch memory cell 20-i via main bit lines BLi and BLi.During the read cycle control signal φW for write transfer gate 60-i isat VDD or (3/2) VDD so that data at nodes Ci and Ci are transferred tonodes Ai and Ai via write transfer gate 60-i which is turned on.

Thereafter latch memory cell activation signal φCE goes from (1/2) VDDto VDD, while activation signal φCE goes from (1/2) VDD to VSS. Duringthat transfer of data, main bit lines BLi and BLi make the respectivetransitions to VDD and VSS. Before the complete transitions of the mainbit lines, control signal DSj for select gate 80-ij and control signalφT for first transfer gate 30-i are lowered from VDD to VSS so as toelectrically disconnect divided bit lines DBij and DBij and latch memorycell 20-i from main bit lines BLi and BLi. This is done to speed up thelatch operation, to reduce the power dissipation and to speed up therewrite (restore) operation for the dRAM cells.

The disconnected main bit lines BLi and BLi are precharged to (1/2) VDDbecause main bit-line equalize signal EQL1 goes from VSS to VDD.Depending on the array arrangement and the memory capacitance, thecapacitance of the main bit lines will be above 2pF in the case of a16-Mbit dRAM, for instance. The restoring of the dRAM cells by thedivided bit lines and latching of data by the latch memory cell underthe condition of connection of the main bit-line capacitance would notonly take a time but also require the large dissipation of power inorder to charge and discharge main bit lines BLi to VDD and VSS. In thisrespect, this embodiment is arranged to precharge main bit lines BLi andBLi before the transitions thereof to VDD and VSS, resulting in reducedpower dissipation. The final precharge levels of main bit lines BLi andBLi are (1/2) VDD+α and (1/2) VDD-α, respectively. α may be about (1/10)VDD.

Thereafter divided bit lines DBij and DBij go to VDD and VSS,respectively. After dRAM cells have sufficiently been restored, selectedword line MWj1 and dummy word line DWj2 are lowered from (3/2) VDD toVSS, going into nonselected state.

Divided bit line equalize signal EQLj and dummy cell equalize signalEQL2 subsequently go from VSS to VDD, beginning the equalizing andprecharging of the divided bit lines.

A series of operations of selecting the word line, operating the dividedbit-line sense amplifier, transferring data to the latch memory cell,precharging the main bit lines, resetting the word line and prechargingthe divided bit lines is automatically performed by the RAS going fromlogic "1" to "0".

Independently of the above operation, when, for example, the i-th columnis selected by the CAS going from "1" to "0", column select line CSLigoes from VSS to VDD or (3/2) VDD, electrically connecting nodes Ai andAi to input/output lines I/O and I/O. In this case, I/O remain at VDD,while I/O goes from VDD to VSS, changing output terminal Dout from Hizto logic "1" level.

The RAS subsequently goes from "0" to "1". When CAS goes from "0" to "1"in this state, latch memory cell activation signals φCE and φCE returnto the former (1/2) VDD, resetting all the latch memory cells.

FIGS. 23A and 23B show signal waveforms representing the operationduring a write cycle of the dRAM of the present embodiment. During thewrite cycle, CAS goes from logic "1" to logic "0" prior to RAS, and atthe same time main bit-line precharge signal EQL1 goes from VDD to VSS,causing main bit lines BLi and BLi to go into the floating state. Thecolumn address buffer is also rendered operative so that a columnaddress is loaded.

If, for example, the i-th column is selected by the column address, thencolumn address CSLi goes from VSS to VDD or (3/2) VDD, turning secondtransfer gate 40-i on. At the same time first transfer gate 30-i is alsoturned on by the rise of control signal φT. Write trigger signal WEbecomes "0" simultaneously with CAS, and control signal φW goes to VSSso that write transfer gate 60-i is turned off.

As a result, latch memory cell 20-i is electrically disconnected frommain bit lines BLi and BLi. At the same time the write circuitryoperates to activate the sense amplifier of input/output lines I/O andI/O. If write input data "0", I/O goes from VDD to VSS, while I/Oimmediately returns to VDD after being slightly lowered becauseelectrons flow into the bit line BLi.

In this way the write data is transferred from input/output lines I/Oand I/O to main bit lines BLi and BLi. Bit line BLi goes from (1/2) VDDto VSS, while bit line BLi goes (1/2) VDD to VDD or VDD-Vth.

Thereafter, when RAS goes "1" to "0", the row address buffer operates sothat a row address is loaded. Assuming now that the j-th bit-line pairis selected by the row address, divided bit-line equalize signal EQL4jand dummy cell equalize signal EQL2 go from VDD to VSS so that thedivided bit-line pair goes into the floating state. Thereafter word lineMWj1 and dummy word line DWi2 go in level from VSS to (3/2) VDD or VDD.

Thereafter n-channel transistor activation signal φSEj for the dividedbit-line sense amplifier goes from (1/2) VDD to VSS, while p-channeltransistor activation signal φSEj subsequently goes from (1/2)VDD toVDD. Divided bit line DBij onto which "1" data was read from memory cellMij1 goes to VDD, while divided bit line DBij onto which data has beenread out of dummy cell Dij2 goes to VSS. During the level transition ofthe divided bit lines, divided bit-line select signal DSi goes from VSSto VDD so that write data on main bit lines BLi and BLi are transferredto divided bit lines DBij and DBij via select gate 80-ij. In this case,since the write data is "0", as opposed to "1" which has previously beenstored, a potential relationship between divided bit lines DBij and DBijis reversed with the result that DBij go from VDD to VSS, while DBijgoes from VSS to VDD.

Divided bit-line select signal DSi and first transfer gate controlsignal φt are lowered from VDD to VSS before main bit lines BLh and BLhfor nonselected columns make complete transitions to VDD and VSS,respectively. Consequently, divided bit lines DBih and DBih areelectrically disconnected from main bit lines BLh and BLh. This is done,as in the read cycle, to speed up the rewriting of memory cells and toreduce power dissipation.

All of the selected j-th divided bit lines DBj and DBj subsequently goto VDD and VSS, respectively, and when the memory cells connected to aselected word line are sufficiently rewritten into, selected word lineMWj1 and dummy word line DWj2 are reset from (3/2) VDD to VSS.

Next divided bit-line equalize signal EQL4 goes from VSS to VDD toinitiate the equalizing and precharging of the divided bit lines.Thereafter WE, RAS and CAS go from logic "0" to logic "1", writetransfer-gate control signal φW goes from VSS to VDD, and column addresssignal CSLi goes to VSS so that input/output lines I/O, I/O and writenodes Ci, Ci are reset.

In the read mode of operation, RAS precedes CAS. When the delay of CASis small, the column address-buffer control signal is gated withoutrising until clocks for RAS informing that the row address has beenloaded rise. Conversely, in the write mode of operation, CAS precedesRAS. When the delay of RAS is small, the row address-buffer controlsignal is gated without rising until clocks for CAS informing that thecolumn address has been loaded rise.

As described above, according to the sixth embodiment, a plurality ofdivided bit-line pairs are connected to a main bit-line pair, dRAM cellsare connected to each divided bit-line pair, and a latch memory cell isconnected to the main bit-line pair. Data can, therefore, be transferredbetween the dRAM chip and the outside during the precharge period.Hence, since there is no need for the RAS precharge period, the cycletime can be shortened. In addition, the latch operation of the latchmemory cell and the rewrite operation for the dRAM cells by means of thedivided bit lines can be speeded up, and since the main bit lines neednot be charged or discharged completely, the power dissipation can bereduced. Furthermore, the latch memory cell is connected to the writenodes via the write transfer gate, and the write nodes are furtherconnected to the main bit lines and the input/output lines via first andsecond transfer gates. Thus, in the write cycle, by turning the writetransfer gate off and turning the first and second transfer gates on sothat the input/output lines may be electrically connected to the mainbit lines, and further, in this case, by causing CAS to precede RAS sothat the column address may be loaded prior to the row address, it ispossible to write data at high speed.

As described above, according to the present invention, a dynamic RAMcan be provided which can reduce the cycle time by precharging the bitlines during the RAS active period.

Although the preferred embodiments of the present invention have beendisclosed and described, it is apparent that other embodiments andmodifications are possible. For example, modifications of an embodimentmay be applied to the other embodiments.

What is claimed is:
 1. A semiconductor memory device comprising:aplurality of bit lines and a plurality of word lines disposedperpendicular to one another on a semiconductor substrate; a pluralityof dynamic memory cells disposed at intersections of said bit lines andsaid word lines; equalizer means connected to said bit lines; senseamplifier means connected to said bit lines; latch means connected tosaid bit lines; and means, for, when a row address strobe signal forloading a row address into the memory device is active during a readcycle, selecting a word line, causing said latch means to latch dataread from memory cells connected to the selected word line, then ceasingthe selection of said word line, and causing said equalizer means topreset a level of the bit lines.
 2. A semiconductor memory deviceaccording to claim 1, wherein said latch means is a static memory cellconsisting of a flip-flop, said static memory cell being connected to acorresponding bit line via a first transfer gate and to an input/outputline via a second transfer gate; wherein said first transfer gate isrendered conductive for a fixed time after the word line selection andsaid second transfer gate is rendered conductive by a column selectsignal selected when a column address strobe signal for loading a columnaddress signal into the semiconductor memory device is active.
 3. Asemiconductor memory device according to claim 1, wherein said senseamplifier means is used as said latch means, and said sense amplifiermeans is a flop-flop connected to a corresponding bit line via a firsttransfer gate and to an input/output line via a second transfer gate,wherein said first transfer gate being rendered conductive for a fixedtime after the word line selection, and said second transfer gate beingrendered conductive by a column select signal selected when a columnaddress strobe signal for loading a column address signal into thesemiconductor memory device is active.
 4. A semiconductor memory deviceaccording to claim 1, further comprising:means for serially accessingmemory cell data latched into said latch means during the row addressstrobe signal's active period, by changing the level of the columnaddress strobe signal for loading the column address signal into thesemiconductor memory device.
 5. A semiconductor memory device accordingto claim 1, wherein each of said bit lines comprises a plurality ofdivided bit lines to which a plurality of memory cells are connected anda main bit line to which said divided bit lines are connected via selectgates; said sense amplifier means comprises divided bit line senseamplifiers each provided for each of said divided bit lines; and saidlatch means is connected to said main bit lines via first transfer gateswhich are rendered conductive after the word line selection andconnected to input/output lines via second transfer gates which arerendered conductive by a column select signal selected when a columnaddress strobe signal for loading a column address signal into thesemiconductor memory device is active.
 6. A semiconductor memory deviceaccording to claim 5, further comprising:means for preventing thepotential of said main bit lines from becoming a power source potentialwhen data in a memory cell is transferred from a divided bit line tosaid latch means via said main bit line.
 7. A semiconductor memorydevice according to claim 5, further comprising:means for seriallyaccessing memory cell data latched into said latch means during the rowaddress strobe signal's active time period by changing the level of thecolumn address strobe signal for loading the column address signal intothe semiconductor memory device.
 8. A semiconductor memory deviceaccording to claim 5, in which, in a read mode of operation, the rowaddress strobe signal becomes active, the column address strobe signalbecomes active, a signal informing that the row address has been loadedbecomes active and a column address-buffer control signal is generatedand, in a write mode of operation, the column address strobe signalbecomes active, the row address strobe signal becomes active, a signalinforming that the column address has been loaded becomes active, and arow address-buffer control signal is generated.
 9. A semiconductormemory device according to claim 1, wherein an address multiplexingsystem is used in which a column address for selecting a bit line and arow address for selecting a word line are entered into said memorydevice via the same address terminals thereof, and wherein, both in aread cycle and in a write cycle, a column address is loaded by thecolumn address strobe signal and then a row address is loaded by the rowaddress strobe signal.
 10. A semiconductor memory device comprising:aplurality of bit lines and a plurality of word lines disposedperpendicular to one another on a semiconductor substrate; a pluralityof dynamic memory cells disposed at intersections of said bit lines andsaid word lines; and plural latch means connected to said bit lines forprecharging said bit lines during a row address strobe signal's activeperiod, each of said latch means being connected to a pair of writenodes via a write transfer gate, each of said pair of write nodes beingconnected to the bit lines via a first transfer gate pair and to aninput/output line via a second transfer gate.
 11. A semiconductor memorydevice according to claim 10, wherein, in a read cycle, the row addressstrobe signal for loading the row address signal into the semiconductormemory device is rendered active prior to a column address strobe signalfor loading a column address signal into the semiconductor memory deviceso that a row address is loaded prior to a column address, and wherein,in a write cycle, the column address strobe signal is rendered activeprior to the row address strobe signal so that a column address isloaded prior to a row address.
 12. A semiconductor memory deviceaccording to claim 10, wherein, when the row address strobe signal forloading a row address signal into the semiconductor memory device isactive in a read cycle, a word line is selected, the selection of theword line is ceased after data in memory cells connected to the wordline is latched into said latch means, and the bit line is precharged byan equalizer; and, when after the row address strobe signal becomesnonactive and a column address strobe signal for loading a columnaddress signal into the semiconductor memory device is active, when acolumn is selected, data in a sense amplifier is read out onto saidinput/output line irrespective of the precharging of said bit line. 13.A semiconductor memory device according to claim 10, wherein, when acolumn address strobe signal for loading a column address signal intothe semiconductor memory device is active in a write cycle, when a writeenable signal is rendered active, a column address is loaded, said writetransfer gate is turned off, a column select line is selected by thecolumn address, and data on said input/output line is transferred tosaid bit line via said first and second transfer gate; and when the rowaddress strobe signal for loading a row address signal into thesemiconductor memory device is active, a word line is selected by a rowaddress, data on said bit line is written into a selected memory cell,said write transfer gate is turned on to connect said latch means tosaid bit line, rewrite said selected memory cell, reset said word lineand precharge said bit line.
 14. A semiconductor memory device accordingto claim 10, wherein said latch means is a static memory cell consistingof a flip-flop.
 15. A semiconductor device according to claim 10,further comprising a sense amplifier which is used for each of saidlatch means.
 16. A semiconductor memory device according to claim 10,further comprising:means for serially accessing memory cell data latchedinto said latch means when the row address strobe signal is active, bychanging the level of the column address strobe signal.
 17. Asemiconductor memory device according to claim 10, wherein each of saidbit lines comprises a plurality of divided bit lines to which aplurality of memory cells are connected and a main bit line to whichsaid divided bit lines are connected via select gates; said senseamplifier comprises a divided bit line sense amplifier provided for eachof said divided bit lines; and said latch means is connected to saidmain bit line via a first transfer gate which is rendered conductiveafter the word line selection and connected to input/output lines via asecond transfer gate which is rendered conductive by a column selectsignal selected when a column address strobe signal for loading a columnaddress signal into the semiconductor memory device is active.
 18. Asemiconductor memory device according to claim 17, furthercomprising:means for preventing the potential of said main bit linesfrom becoming a power source potential when data in said memory cell istransferred from a divided bit line to said latch means via said mainbit line.
 19. A semiconductor memory device according to claim 17,further comprising:means for serially accessing memory cell data latchedinto said latch means when the row address strobe signal is active, bychanging the level of the column address strobe signal.
 20. Asemiconductor memory device according to claim 17, in which, in a readmode of operation, the row address strobe signal becomes active, thecolumn address strobe signal becomes active, a signal informing that therow address has been loaded becomes active, and a column address-buffercontrol signal is generated and, in a write mode of operation, thecolumn address strobe signal becomes active, the row address strobesignal becomes active, a signal informing that the column address hasbeen loaded becomes active, and a row address-buffer control signal isgenerated.
 21. A semiconductor memory device comprising:a plurality ofbit lines and a plurality of word lines disposed perpendicular to oneanother on a semiconductor substrate; a plurality of dynamic memorycells disposed at intersections of said bit lines and said word lines;means, connected to said bit lines, for presetting an initial level ofthe bit lines; sense amplifier means connected to said bit lines; latchmeans connected to said bit lines; and means for, when a row addressstrobe signal for loading a row address into the memory device is activeduring a read cycle, selecting a word line, causing said latch means tolatch data read from memory cells connected to the selected word line,then ceasing the selection of said word line, and causing saidpresetting means to preset the initial level of the bit lines.